CEA-Leti has scaled ferroelectric RAM (FeRAM) to the 22nm node by replacing traditional planar capacitors with a vertical 3D architecture, a breakthrough presented at the VLSI 2026 symposium in Honolulu. The innovation eliminates the density barrier that long prevented FeRAM from competing with volatile memories like SRAM. Using hafnium zirconium oxide (HZO) thin films, the team built capacitors upward, producing memory cells 2.5 times smaller than standard 22nm SRAM and matching the density of 10nm SRAM—while retaining data without power. This non-volatile, high-density memory enables direct embedding on processors, allowing edge devices to process AI locally, cutting energy and time spent on cloud offloading.

The researchers demonstrated two back-end-of-line integration schemes for 3D ferroelectric capacitors (FeCaps) at 22nm. Functional 1T-1C arrays with Gaussian bit distributions were confirmed at 0.047 μm² bitcells operating at just 1.3V, using a standard logic selector and a 3D FeCap with a roughly 4:1 aspect ratio. A path to far denser arrays was also shown: FeCaps with a 17:1 aspect ratio, 60nm diameter, and 120nm pitch shrink the capacitor footprint to 0.0028 μm². The tall, narrow geometry maximizes effective surface area, widening the memory window without sacrificing array density.

Critically, these high-aspect-ratio capacitors displayed no wake-up effect—a common reliability problem where early electrical cycling shifts device characteristics unpredictably. Precession electron diffraction revealed an approximately 80% orthorhombic phase fraction in the HZO film, suggesting that material confinement in the narrow vias modifies strain and stabilizes the memory-active crystal phase from the outset. CEA-Leti plans to integrate such high-aspect-ratio FeCaps into dense arrays on a 22nm FDSOI platform, aiming for the highest-performance embedded FeRAM yet. The research was funded by the European Union, the Chips Joint Undertaking (Fames projects), and French authorities under France 2030 (particularly the NextGen project).

​​​​​​​​​​​Breakthrough Reported at VLSI 2026 Also Extends to High-Performance Computing, Aerospace & Defense Systems, and IoT Platforms​

​HONOLULU, Hawaii — June 15, 2026— CEA-Leti today announced a major advance in memory technology: the demonstration of ferroelectric RAM (FeRAM) scaled to the 22nm manufacturing node using an innovative 3D capacitor architecture. The breakthrough, presented at the VLSI Conference in Honolulu, removes a longstanding density barrier that has kept FeRAM from competing with volatile memory—and opens the door to faster, more energy-efficient artificial intelligence (AI) at the edge.

By vertically integrating ferroelectric capacitors made from hafnium zirconium oxide (HZO) thin films, the team achieved memory cells that are 2.5 times smaller than standard SRAM at the same 22nm node, matching the density of SRAM at the much more advanced 10nm node. Moreover, unlike SRAM, FeRAM retains data without power, combining non-volatility with a density previously attainable only by volatile memory.

Today's smart devices increasingly rely on sending da​ta to the cloud for AI processing—a costly cycle in both time and energy. FeRAM that is both fast and dense enough to embed directly on a processor enables devices to process data locally. The implications extend beyond user convenience: computing operations account for a significant and growing share of global electricity consumption, much of it still generated from fossil fuels.

Historically, FeRAM fabrication was constrained to flat, planar capacitor structures that limited how small and dense memory cells could be manufactured. In these architectures, the capacitor—not the selection transistor—determines the cell footprint because the current flowing through the capacitor during memory operations is inherently low. To overcome this physical limit, CEA-Leti shifted to a vertical architecture, building the capacitor upwards rather than outwards.

The team demonstrated two back-end-of-line (BEOL) integration schemes for 3D ferroelectric capacitors (FeCaps) at 22nm, utilizing advanced patterning and deposition techniques. Array functionality with Gaussian bit distributions was confirmed down to 0.047 μm² 1T-1C FeRAM bitcells operating at just 1.3V, featuring a standard logic selector and a 3D FeCap with an aspect ratio of roughly 4:1.

The researchers also demonstrated a clear path to even greater density: 3D FeCaps with an aspect ratio of 17:1, a 60nm diameter, and a 120nm pitch - shrinking the capacitor footprint to just 0.0028 μm². A higher aspect ratio maximizes the effective surface area of the ferroelectric capacitor within each bitcell, enlarging the memory window without sacrificing array density.

Traditional FeRAM devices often exhibit a phenomenon known as "wake-up," where electrical characteristics shift unpredictably during initial cycling, degrading stability and reliability. CEA-Leti's high-aspect-ratio 3D capacitors exhibited wake-up-free behavior consistent with an approximately 80 percent orthorhombic phase fraction in the HZO film, as confirmed by precession electron diffraction (PED).

While the precise mechanism is still under study, the suppression of wake-up is likely related to the confinement of materials within the narrow, high-aspect-ratio vias, which locally modifies the strain state in the ferroelectric thin film. This stabilizes the crystal phase responsible for memory function from the outset.

CEA-Leti plans to integrate the demonstrated high-aspect-ratio ferroelectric capacitors into dense FeRAM arrays on a 22nm FDSOI platform, aiming to achieve the highest-performance embedded FeRAM to date.

NOTE:Dr.Madjid Hihi,Deputy Director for Clinical Innovation at CEA-Leti's Innovative Health Technologies Division, will speak at a VLSIluncheon from ​​​12:15–1:15 PM,onJune 18. The title of his talk is “Innovative Neurotechnologies – A Journey from the Lab to the Clinic and Back." Neurotechnology is a booming field, andMadjid will highlight clinical world premieres enabled by CEA-Leti technologies.

This project received funding from the European Union and Chips Joint Undertaking (Fames projects), supported by French public authorities (France 2030, in particular through the NextGen project).​