马纳萨·马德瓦拉吉（RMS团队）论文答辩：GHz频率下亚皮秒分辨率随机抖动测量的自参考BIST技术
Thesis defence of Manasa Madhvaraj (RMS team): Self-referenced BIST for random jitter measurement with sub-picosecond resolution at GHz frequency
法国博士生Manasa Madhvaraj（RMS团队）成功完成论文答辩，其研究主题为"GHz频率下亚皮秒分辨率的随机抖动自参考BIST测量技术"。该技术通过创新的自参考内置自测试（BIST）方案，实现了对高速信号随机抖动的高精度测量，有望提升集成电路测试效率与可靠性。
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查看原文Manasa Madhvaraj from the RMS team defended her thesis on a novel built-in self-test (BIST) method for measuring random jitter in high-speed circuits. The research achieves sub-picosecond resolution at GHz frequencies, which is critical for advancing the performance and reliability of next-generation semiconductor devices. This work addresses key challenges in integrated circuit testing, potentially improving quality control for high-frequency applications like processors and communication systems.
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Read originalManasa Madhvaraj, de l'équipe RMS, a soutenu sa thèse sur une méthode BIST auto-référencée pour mesurer le gigue aléatoire avec une résolution sub-picoseconde à des fréquences GHz. Ce travail, mené au sein d'une équipe de recherche spécialisée, vise à améliorer la précision des tests intégrés des circuits haute performance. L'avancée technologique présente un impact significatif pour la caractérisation des systèmes électroniques rapides, notamment dans les domaines des télécommunications et du calcul.
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Lire l'originalCore Point
A researcher successfully defended a thesis on a novel self-referenced Built-In Self-Test (BIST) circuit that can measure random jitter with sub-picosecond resolution at GHz frequencies, advancing high-speed signal integrity testing.
Key Players
Manasa Madhvaraj (RMS team) — Researcher presenting the thesis on integrated circuit testing technology, presumably based in France.
Industry Impact
- ICT: High — Enables more precise on-chip jitter measurement for communication systems.
- Computing/AI: Medium — Critical for high-performance computing and data center interconnects.
Tracking
Monitor — The technology is a specialized R&D advancement with potential long-term implications for chip design and validation.
Highlights
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