At IRPS 2026, the premier forum for microelectronics reliability research, CEA-Leti will present seven papers that underscore its broad, integrated expertise across device physics, process integration, RF technologies, FD-SOI, GaN, BEOL reliability and low-temperature platforms for 3D sequential integration. The Grenoble-based institute says its researchers combine advanced characterization with physics-based modeling to deliver early-stage reliability insights that help both technology developers and circuit designers move toward robust, industrial-grade solutions. CEA-Leti engineers also contributed to two additional projects that will be presented at the symposium.

One of the most application-oriented papers, “RF Aging Extensive Characterization & Modeling for Reliability-Aware Power Amplifier Design,” will be presented on Thursday, March 26, from 1:35 to 2:00 PM by Tarek Daher and Alexis Divay in collaboration with STMicroelectronics. The work introduces a methodology that directly measures hot-carrier-induced lifetime in standalone SOI power amplifiers under realistic RF stress, including varied bias conditions and load-impedance mismatches. By producing empirical time-to-failure contour maps, the team gives designers an immediate view of the trade-off between performance and reliability during early PA design for mmWave 5G and beyond-5G systems.

CEA-Leti will also highlight progress on GaN integration with “Thermal Robustness of a CMOS-Compatible GaN-on-Si MIS-HEMT Technology,” scheduled for Thursday, March 26, from 3:25 to 3:50 PM. After 1,400 hours of unbiased storage at temperatures up to 375°C, 0.15 µm SiN/InAlN/GaN MIS-HEMTs showed only a modest threshold-voltage shift of about -200 mV, roughly a 20% increase in contact resistance, and small reductions in drain current and transconductance. Microscopy found no side-wall interdiffusion, which the institute attributes to the use of a refractory alloy gate. The result supports the case for monolithic GaN power blocks on silicon for high-temperature automotive and aerospace electronics.

In BEOL reliability, the paper “Improving Electromigration Lifetime Through Power-Grid Segmentation: An Experimental Study,” presented Thursday, March 26, from 2:00 to 2:25 PM, shows how segmentation can extend lifetime. Robert Bloom of the University of Minnesota, with contribution from Stéphane Moreau of CEA-Leti, used silicon-level electromigration tests on segmented power-grid structures to exploit the Blech effect. Shorter segments reduced stress-migration-driven void formation, leading to significantly longer time-to-failure and smaller IR-drop shifts. The finding positions power-grid segmentation as a practical layout-level lever for improving electromigration robustness in advanced nodes carrying high current.

Several papers focus on degradation mechanisms in SOI and FD-SOI devices. “Influence of Channel Doping on HCI Degradation in Analog SOI nMOSFETs,” presented Tuesday, March 24, from 4:30 to 4:55 PM, combines TCAD simulations with experiments to show that lower channel doping expands the impact-ionization region, increasing hot-carrier generation and interface-trap formation in nitrided SiO2-gate SOI nMOSFETs. By incorporating channel implantation dose into the Takeda model, the researchers accurately predict the observed rise in time-to-failure, offering analog designers a way to mitigate HCI through doping-profile optimization.

Another study, “Dit-Nt Correlation in pBTI Stressed SOI nMOSFET via Low Frequency Noise Measurements,” presented Tuesday, March 24, from 2:00 to 2:25 PM, uses low-frequency-noise measurements to show that as pBTI stress progresses, oxide-trap density (Nt) rises in lockstep with interface-trap density (Dit). The strong correlation suggests that interface quality is the dominant factor in stress-induced noise, reinforcing the need for robust interface engineering in future FD-SOI devices.

CEA-Leti is also presenting work on spacer materials and gate-stack scaling. “Spacer Trapping Effect on Hot-Carrier Degradation Dynamics for Advanced FD-SOI Nodes,” scheduled for Wednesday, March 25, from 2:00 to 2:25 PM, compares high- and low-trapping SiCO spacers. The study finds that trapped charge in spacers dominates early HCI wear but saturates quickly, while low-trapping spacers completely suppress this early degradation. The implication is that spacer material choice is a key lever for extending lifetime in future GAA and CFET platforms.

In “Modeling the Impact of HK Thickness Scaling (Down to 1.1 nm) on Gate Leakage and PBTI in Advanced FD-SOI Devices,” presented Tuesday, March 24, from 4:05 to 4:30 PM, Elhadji Alhousseyni Diallo uses direct-tunnelling physics and Comphy simulations to quantify how ultra-thin high-k layers affect gate leakage and positive-bias-temperature-instability. The study finds that a higher tunnel mass in sub-2 nm oxides points to a microstructural shift, while reduced high-k thickness simultaneously lowers leakage and improves PBTI endurance. The result is a calibrated model intended to guide designers as they push high-k scaling in next-generation FD-SOI technologies.

Two additional papers extend CEA-Leti’s reach into RF noise and 3D sequential integration. “Ground-Plane Effect on Random Telegraph Noise in Mesa-Isolated SOI MOSFETs for 3D Sequential CISi,” presented Tuesday, March 24, from 11:20 to 11:45 PM, with authors Ahmed Machmach of STMicroelectronics and contributions from Joris Lacord and Fabienne Ponthenier of CEA-Leti, shows that increasing substrate or ground-plane bias reshapes the channel electric field. This pushes more oxide-trap events above the detection threshold and amplifies current spikes, creating a controllable RTN boost that can help designers predict and mitigate noise in 3D sequential CMOS image sensors.

Finally, “Thermal Robustness of a CMOS-Compatible GaN-on-Si MIS-HEMT Technology” and the other reliability studies are supported by NexGen 2030, FAMES Pilot Line and IRT Nanoelec, reflecting the broader ecosystem backing CEA-Leti’s work. Taken together, the seven papers present a consistent message: reliability can be engineered earlier in the design flow through better modeling, better materials and better layout choices, whether the target is RF power amplifiers, advanced logic, image sensors or high-temperature power electronics.

RPS - International Reliability Physics Symposium

Seven Papers Present Early‑Stage Insights to Guide Technology Developers And Circuit Designers Toward Robust, Industrial‑Grade Solutions​

​​​GRENOBLE, France — March 17, 2026 — AtIRPS 2026, the premier forum for new and original research in microelectronics reliability, CEA‑Leti will present seven papers that reflect a broad and integrated expertise across device physics, process integration, RF technologies, FD‑SOI, GaN, BEOL reliability, and low‑temperature platforms enabling 3D sequential integration. Institute research engineers also contributed to two other projects whose work will be presented.

The papers demonstrate the institute's ability to combine innovative characterization methods with physics‑based modelling, delivering early‑stage reliability insights that guide both technology developers and circuit designers toward robust, industrial‑grade solutions.

“RF Aging Extensive Characterization & Modeling for Reliability‑Aware Power Amplifier Design"

Thursday, March 26, 1:35‑2:00 PM

Authors: Tarek Daher, Alexis Divay in collaboration with STMicroelectronics

A novel methodology directly measures hot‑carrier‑induced (HCI) lifetime of standalone SOI power amplifiers under realistic RF stress, covering varied bias conditions and load‑impedance mismatches. Empirical time‑to‑failure contour maps are generated, giving designers immediate visibility into performance‑reliability trade‑offs during early PA design for emerging mmWave 5G and beyond‑5G applications.​

“Thermal Robustness of a CMOS‑Compatible GaN‑on‑Si MIS‑HEMT Technology"

Thursday, March 26, 3:25‑3:50 PM

1,400 h, up‑to‑375 °C unbiased storage tests on 0.15 µm SiN/InAlN/GaN MIS‑HEMTs (CMOS‑compatible) show only modest Vth shift (≈‑200 mV), ~20 % contact‑resistance rise, and small drops in Id and gm. Microscopy confirms no side‑wall interdiffusion thanks to a refractory alloy gate. The devices remain electrically stable at extreme temperatures, proving GaN power blocks can be monolithically integrated on silicon for high‑temperature automotive or aerospace electronics.

“Reaching the BTI 10‑Year Lifetime for 2.5 V BEOL‑Compatible (2.5‑rated CMOS that can be stacked in 3D sequential processes without exceeding 420 °C.

“Influence of Channel Doping on HCI Degradation in Analog SOI nMOSFETs"

Tuesday, March 24, 4:30‑4:55 PM

TCAD simulations and experimental validation show that lower channel doping expands the impact‑ionization region, increasing hot‑carrier generation and interface‑trap formation in nitrided SiO₂‑gate SOI nMOSFETs. Incorporating the channel implantation dose into the Takeda model accurately predicts the observed rise in time‑to‑failure, providing a clear path for analog designers to mitigate HCI by tailoring doping profiles.

“Improving Electromigration Lifetime Through Power‑Grid Segmentation: An Experimental Study"

Thursday, March 26, 2:00‑2:25 PM

Authors: Robert Bloom (University of Minnesota) with contribution from Stéphane Moreau (CEA-Leti)

Silicon‑level EM tests on segmented power‑grid structures exploit the Blech effect: shorter segments reduce stress‑migration‑driven void formation, yielding markedly longer time‑to‑failure and smaller IR‑drop shifts. Segmenting BEOL power grids becomes a practical, layout‑level knob to boost EM robustness in advanced nodes carrying high currents.

“Ground-Plane Effect on Random Telegraph Noise in Mesa-Isolated SOI MOSFETs for 3D Sequential CISi"

Tuesday, March 24, 11:20‑11:45 PM

Authors: Ahmed Machmach (STMicroelectronics) with contribution from Joris Lacord and Fabienne Ponthenier (CEA-Leti)

Increasing the substrate (ground‑plane) bias reshapes the channel's electric field, pushing more oxide‑trap events above the detection threshold and amplifying their current spikes. This controllable RTN boost helps designers predict and mitigate noise in 3‑D sequential CMOS image sensors.

“Dit-Nt Correlation in pBTI Stressed SOI nMOSFET via Low Frequency Noise Measurements"

Tuesday, March 24, 2:00-2:25 PM

Low‑frequency‑noise measurements show that as pBTI stress progresses, oxide‑trap density (Nt) rises in lockstep with interface‑trap density (Dit). The tight correlation indicates that interface quality dominates stress‑induced noise, emphasizing the need for robust interface engineering in future FD‑SOI devices.

“Spacer Trapping Effect on Hot‑Carrier Degradation Dynamics for Advanced FD‑SOI Nodes"

Wednesday, March 25, 2:00‑2:25 PM

Comparing high‑ vs. low‑trapping SiCO spacers reveals that trapped charge in spacers dominates early HCI wear but saturates quickly; low‑trapping spacers completely suppress this early degradation. Spacer material selection is a decisive lever for extending device lifetime in forthcoming GAA and CFET platforms.​

“Modeling the Impact of HK Thickness Scaling (Down to 1.1 nm) on Gate Leakage and PBTI in Advanced FD‑SOI Devices"

Tuesday, March 24, 4:05‑4:30 PM

Author: Elhadji Alhousseyni Diallo

Using direct‑tunnelling physics and Comphy simulations, this study quantifies how ultra‑thin high‑k (HK) layers affect gate leakage and positive‑bias‑temperature‑instability (PBTI). A higher tunnel mass in sub‑2 nm oxides indicates a microstructural shift, while reduced HK thickness simultaneously lowers leakage and improves PBTI endurance. The results provide a calibrated model that designers can employ when pushing HK scaling for next‑generation FD‑SOI technologies.​​

This work was supported by NexGen 2030, FAMES Pilot Line and IRT Nanoelec.​​