CEA-Leti has demonstrated a functional test vehicle using die-to-wafer (D2W) hybrid bonding with pitches down to 1 µm, presented at ECTC 2026. As Moore’s Law reaches its limits, 3D integration becomes essential for high-performance computing, AI accelerators, and smart-vision systems. This D2W technique tackles the critical bottleneck of interconnect density and bandwidth by vertically stacking device layers with ultra-fine pitches, shortening interconnect paths to boost data transfer speeds and cut power consumption.

Engineering 1 µm pitch required precise alignment accuracy—the main challenge—and optimized chemical mechanical planarization (CMP) for the inter-die gap filling (IDGF) used during wafer reconstruction, ensuring compatibility with later vertical interconnects. Electrical characterization of daisy-chain structures confirmed expected performance and yields for pitches from 5 µm down to 2 µm. At 1 µm, yield was limited by the alignment accuracy of current bonding tools, but next-generation tools with 0.5 µm (3σ) alignment capability are expected to bring significant improvements.

This proof of concept is transitional, laying the foundation for a second-generation test vehicle that will integrate D2W with high-density through-silicon vias (HD TSV) and through-oxide vias (TOV) via the IDGF step, enabling dense vertical interconnection of different dies and functions. The D2W work was conducted under the FAMES Pilot Line and ANR NextGen project (France 2030 initiative), while related IDGF, TOV, and HD TSV studies were supported by IRT Nanoelec.

CEA-Leti has over 15 years of expertise in hybrid bonding (wafer-to-wafer and D2W) and HD TSV, particularly for three-layer CMOS image sensors at IRT Nanoelec. In 2024, it earned highlighted-paper recognition at ECTC for a three-layer test vehicle with two embedded Cu-Cu hybrid-bonding interfaces (face-to-face and face-to-back) and a wafer with HD TSVs. The project is funded by the European Union, Chips Joint Undertaking, and French public authorities including France 2030 through IRT Nanoelec, IPCEI ME, and the NextGen project.

Communiqué de presse|Actualité|Nouvelles technologies

ORLANDO, Fla.– May 29, 2026 – CEA-Leti today announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1 μm. The findings were presented at the Electronic Components and Technology Conference (ECTC) 2026.

As Moore's Law reaches physical limits, the semiconductor industry is increasingly relying on 3D stacking to enhance performance and energy efficiency. This D2W technology addresses a critical bottleneck in AI accelerator design: interconnect density and bandwidth. By vertically stacking device layers with ultra-fine pitches, the technology shortens interconnect paths, significantly increasing data transfer speeds while reducing power consumption.

Achieving a 1 μm pitch required the team to engineer very precise alignment accuracy, the primary challenge for the D2W building block. Additionally, the wafer reconstruction process involving inter-die gap filling (IDGF) demanded optimized chemical mechanical planarization (CMP) to ensure compatibility with subsequent vertical interconnects.

Electrical characterization of daisy-chain structures confirmed expected performance and yields for pitches ranging from 5 μm down to 2 μm. While the yield at 1 μm is limited by the alignment accuracy of existing bonding tools, the team anticipates significant improvements with the introduction of next-generation tools featuring 0.5 μm (3σ) alignment capabilities.

This demonstration serves as a transitional proof of concept, laying the groundwork for a second-generation test vehicle. The immediate next steps include integrating the D2W technology with vertical interconnections—specifically high density through-silicon vias (HD TSV) and through-oxide vias (TOV)—facilitated by the intermediate inter-die gap filling (IDGF) process step.

The building blocks related to IDGF, TOV and HD TSV will enable the integration of different dies and functions with dense vertical interconnections.

The D2W research was carried out within the framework of the FAMES Pilot Line and the ANR NextGen project (France 2030 initiative). Related IDGF, TOV and HD TSV studies were supported by IRT Nanoelec.

A CEA-Leti team has focused for more than 15 years on the key enabling technology of hybrid bonding (W2W and D2W) and HD TSV for the three-layer CMOS image sensors under development at IRT Nanoelec, and it publishes several papers at every ECTC conference. The institute received a highlighted-paper recognition at ECTC 2024 for demonstrating a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and one wafer containing HD TSVs.

​​This project received funding from the European Union and Chips Joint Undertaking (Fames projects), supported by French public authorities (France 2030 in particular through IRT Nanoelec, IPCEI ME and the NextGen project).