CEA-Leti has demonstrated a functional die-to-wafer (D2W) hybrid bonding test vehicle with interconnect pitches down to 1 µm, a milestone presented at ECTC 2026. The advance addresses the critical interconnect density and bandwidth bottleneck in AI accelerators and high-performance computing by enabling 3D stacking with ultra-short, high-speed data paths that also lower power consumption. Achieving 1 µm pitch required exceptional alignment accuracy—the primary D2W challenge—and an optimized chemical mechanical planarization (CMP) step in the wafer reconstruction process’s inter-die gap filling (IDGF). Electrical characterization of daisy-chain structures confirmed expected performance and yields for pitches from 5 µm down to 2 µm; 1 µm yield is currently constrained by the alignment precision of existing bonding tools, but the team expects significant improvement with next-generation tools boasting 0.5 µm (3σ) capabilities. This proof-of-concept will now evolve into a second-generation vehicle that integrates vertical interconnections—high-density through-silicon vias (HD TSV) and through-oxide vias (TOV)—using the IDGF process to combine different dies and functions. The D2W work was carried out under the FAMES Pilot Line and the ANR NextGen project (France 2030), with IDGF, TOV, and HD TSV studies supported by IRT Nanoelec. CEA-Leti has spent over 15 years on hybrid bonding and HD TSV, notably earning a highlighted paper at ECTC 2024 for a three-layer test vehicle with two embedded Cu-Cu hybrid-bonding interfaces. The project received funding from the European Union, Chips Joint Undertaking, and French public authorities via France 2030, IRT Nanoelec, IPCEI ME, and the NextGen project.

ORLANDO, Fla.– May 29, 2026 – CEA-Leti today announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1 μm. The findings were presented at the Electronic Components and Technology Conference (ECTC) 2026.

As Moore's Law reaches physical limits, the semiconductor industry is increasingly relying on 3D stacking to enhance performance and energy efficiency. This D2W technology addresses a critical bottleneck in AI accelerator design: interconnect density and bandwidth. By vertically stacking device layers with ultra-fine pitches, the technology shortens interconnect paths, significantly increasing data transfer speeds while reducing power consumption.

Achieving a 1 μm pitch required the team to engineer very precise alignment accuracy, the primary challenge for the D2W building block. Additionally, the wafer reconstruction process involving inter-die gap filling (IDGF) demanded optimized chemical mechanical planarization (CMP) to ensure compatibility with subsequent vertical interconnects.

Electrical characterization of daisy-chain structures confirmed expected performance and yields for pitches ranging from 5 μm down to 2 μm. While the yield at 1 μm is limited by the alignment accuracy of existing bonding tools, the team anticipates significant improvements with the introduction of next-generation tools featuring 0.5 μm (3σ) alignment capabilities.

This demonstration serves as a transitional proof of concept, laying the groundwork for a second-generation test vehicle. The immediate next steps include integrating the D2W technology with vertical interconnections—specifically high density through-silicon vias (HD TSV) and through-oxide vias (TOV)—facilitated by the intermediate inter-die gap filling (IDGF) process step.

The building blocks related to IDGF, TOV and HD TSV will enable the integration of different dies and functions with dense vertical interconnections.

The D2W research was carried out within the framework of the FAMES Pilot Line and the ANR NextGen project (France 2030 initiative). Related IDGF, TOV and HD TSV studies were supported by IRT Nanoelec.

A CEA-Leti team has focused for more than 15 years on the key enabling technology of hybrid bonding (W2W and D2W) and HD TSV for the three-layer CMOS image sensors under development at IRT Nanoelec, and it publishes several papers at every ECTC conference. The institute received a highlighted-paper recognition at ECTC 2024 for demonstrating a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and one wafer containing HD TSVs.

​​This project received funding from the European Union and Chips Joint Undertaking (Fames projects), supported by French public authorities (France 2030 in particular through IRT Nanoelec, IPCEI ME and the NextGen project).