Amid growing semiconductor supply-chain strain and a drive for technological sovereignty, France has officially launched ASTEERICS, its national Chips Competence Center, funded by the EU’s Chips Joint Undertaking and backed by the French government under the France 2030 plan. The initiative aims to accelerate the uptake of energy-efficient chip technologies among French startups, SMEs, and industrial players.

ASTEERICS is one of 30 competence centers selected in 2025 across 28 European countries under the European Chips Act, intended to elevate the continent’s semiconductor expertise. Led by the Minalogic cluster in partnership with CNFM, Captronic, and five other competitiveness clusters (Aktantis, Alpha-RLH, Images & Réseaux, Smart Power, and Systematic Paris-Région), it serves as a national hub for informing, training, and supporting companies exploring ASIC, ASSP, FPGA, MEMS, or photonics integrated circuit (PIC) projects. Fully woven into the European network, the center will collaborate closely with counterparts to share expertise and coordinate access to EU semiconductor resources—pilot lines, design platforms, and testing infrastructure—beyond national borders.

Many firms still struggle to adopt integrated technologies due to skills gaps, limited visibility into existing solutions, or scarce access to industrial assets. ASTEERICS tackles these roadblocks by concentrating on three homegrown energy-efficient technologies: FDSOI, GaN, and SiC. It will offer awareness and training sessions for decision-makers and engineers, personalized technical and economic guidance to match projects with the right technology and funding opportunities, and priority access to European expertise, tools, and infrastructure.

“ASTEERICS addresses a very concrete need for companies: understanding when and how to transition to chip technologies, and receiving support at every stage, from opportunity analysis to access to pilot lines and funding,” said Hervé Ribot, Director of the competence center and Technology Development Director at Minalogic. “The challenge is not solely technological, it is also economic and strategic. ASTEERICS supports companies in building viable, competitive, and fundable projects.”

Rather than a single physical site, ASTEERICS is a nationally networked initiative drawing on academic, industrial, and institutional partners across multiple regions, with links to European assets such as the FAMES pilot line in Grenoble, the EuroCDP design platform, design houses, foundries, and OSAT providers. The launch was marked by a conference on January 28, 2026, gathering European experts, industry representatives, investors, and institutions to discuss sector challenges, existing infrastructure, and success factors for energy-efficient integrated circuit projects.

Against a backdrop of significant strain on the semiconductor value chain and the growing importance of technological sovereignty, ASTEERICS, the French Chips Competence Center, has been officially launched. Funded by the European Union through the Chips Joint Undertaking and supported by the French government as part of the France 2030 initiative, ASTEERICS aims to accelerate the adoption of energy-efficient chip technologies by French startups, SMEs, and industrial players.

In 2025, 30 chips competence centers across 28 European countries were selected under the European Chips Act, with the aim of taking Europe’s semiconductor expertise to the next level.

Led by Minalogic, in partnership with the CNFM, Captronic, and five other competitiveness clusters (Aktantis, Alpha-RLH, Images & Réseaux, Smart Power, and Systematic Paris-Région), the French competence center ASTEERICS serves as the national hub for informing, training, and supporting companies in their ASIC, ASSP, FPGA, MEMS, or PIC (Photonics Integrated Circuits) projects.

The French competence center is fully integrated into the European network of Chips Competence Centers, strategic components of the European Chips Act, and will develop close collaborations with other European competence centers to foster synergies, the sharing of expertise, and coordinated access to European semiconductor resources (pilot lines and design platforms) beyond national borders.

Addressing a strategic challenge for Europe's industry

While microelectronics lies at the heart of the digital, energy, and industrial transitions, many companies still struggle to make the leap to integrated technologies due to a lack of skills, visibility into existing solutions, or access to industrial resources. ASTEERICS aims to remove these barriers, drawing in particular on three energy-efficient, domestically developed technologies: FDSOI, GaN, and SiC.

ASTEERICS will offer:

awareness-raising and training sessions for decision-makers, entrepreneurs, and engineers,

personalized technical and economic support to identify the technology best suited to growth objectives, structure projects, and facilitate access to financing,

priority access to European expertise, tools, and infrastructure.

“ASTEERICS addresses a very concrete need for companies: understanding when and how to transition to chip technologies, and receiving support at every stage, from opportunity analysis to access to pilot lines and funding,” emphasizes Hervé Ribot, Director of the ASTEERICS Competence Center and Director of Technology Development at Minalogic. “The challenge is not solely technological, it is also economic and strategic. ASTEERICS supports companies in building viable, competitive, and fundable projects,” he continues.

A national and European network of partners

ASTEERICS is not a center physically located at a single site. It is a national networked initiative, supported by an ecosystem of academic, industrial, and institutional partners spread across several regions, and connected to European resources: pilot lines (including FAMES, based in Grenoble), the European design platform EuroCDP, design houses, foundries, and OSATs.

A launch event on January 28th 2026 brought the ecosystem together

The official launch of ASTEERICS featured a day of conferences, roundtables, and experience-sharing sessions bringing together European experts, industry representatives, investors, and institutional stakeholders. Discussions focused in particular on the challenges facing the electronics sector, existing national and European initiatives and infrastructure, as well as the key success factors for projects developing energy-efficient integrated circuits.

Download the press release (French only)

Funded by the European Union. However, the views and opinions expressed are those of the author(s) alone and do not necessarily reflect those of the European Union or the CHIPS Joint Undertaking. Neither the European Union nor the funding authority can be held liable for them.

L’article Launch of ASTEERICS, the French Chips Competence Center est apparu en premier sur Minalogic.