The 11th IEEE Electronics System-Integration Technology Conference (ESTC) returns to Helsinki, Finland, from September 9 to 11, 2026, with CEA-Leti showcasing its latest advances in 3D and heterogeneous integration. At its booth, the French research institute will highlight 3D chiplet integration and discuss three papers spanning substrate innovation, bonding processes, and environmental assessment—addressing applications from high-performance computing and AI to co-packaged optics, RF, quantum computing, and imagers.

On Wednesday, September 9 (3:50–4:15 pm), in the Substrate Innovation session, CEA-Leti will present the development of middle through‑silicon vias (TSV Mid) integrated with advanced SiGe BiCMOS technology for optical interconnects. Thursday’s Advances in Materials and Processes session (4:35–5:00 pm) features heterogeneous integration combining die‑to‑wafer microbump bonding and hybrid copper bonding on a single interposer. On Friday, September 11 (11:00 am–12:15 pm), the same session will examine the environmental footprint of fan‑out wafer‑level packaging technology.

ESTC, chaired this year by Toni Mattila of Business Finland, is the premier European event for electronics packaging and system integration, serving as the IEEE Electronics Packaging Society’s flagship conference on the continent and co-sponsored by IMAPS Europe. Jean‑Charles Souriau, research engineer at CEA-Leti, is the contact for the institute’s presence.

Beyond ESTC, CEA-Leti will engage in several other upcoming forums. The END* symposium at Maison Minatec in Grenoble will tackle sustainable integrated hardware and software for ICT, focusing on frugal, ethical, and data‑sovereign digital solutions. At the LID World Summit (June 23–25), gathering over 1,250 semiconductor professionals, CEA-Leti will present on ferroelectric memories, neurotechnologies, and cryo‑CMOS circuits. PCIM will feature live demonstrations including an ultra‑thin piezoelectric power converter, a smart multilevel converter with flying capacitor topology, a high‑power multilevel GaN DC‑DC converter, and predictive maintenance using non‑invasive sensors, while outlining the institute’s wide‑band‑gap roadmap for power supplies across data center, drone, automotive, aeronautics, space, and medical sectors. Finally, a workshop at Minatec will convene experts in dry etching, plasma processing, and related technologies for semiconductors, MEMS, and emerging applications.

From 9/9/2026 to 9/11/2026Helsinki, Finland

CEA-Leti experts will be onsite at CEA-Leti's booth and available to discuss the findings of three papers on heterogeneous integration​​

COME AND MEET CEA-LETI'S EXPERTS​

This year, CEA-Leti’s booth will exhibit 3D Chiplet integration. Come and discuss lastest achievements in terms of 3D and packaging.​​

CEA-Leti's 3D integration technologies respond to tomorrow’s challenges in a wide range of applications, including high-performance computing (HPC), AI, copackage optics, RF integration, quantum computing, power delivery, and also imagers and displays.​

Wednesday, September 93:50 - 4:15 pmAP 1: Substrate Innovation

Development of Middle Through Silicon Vias (TSV Mid) and Integration in Advanced SiGe BiCMOS Technology for Optical Interconnects

Thursday, September 10​4:35 pm - 5:00 pmAP 5: Advances in Materials and Processes

Heterogeneous Integration of Die to Wafer Microbumps Bonding and Hybrid Cu Bonding on a Single Interposer

Friday, September 1111:00 am - 12:15 ​pmAP 5: Advances in Materials and Processes

Environmental Assessment of the Fan-out Wafer Level Packaging Technology​​

The 11th IEEE Electronics System-Integration Technology Conference will be taking place in Helsinki from September 9-11, 2026. IEEE ESTC is the premier international event in the field of electronics packaging and system integration and the IEEE EPS flagship conference in Europe, co-sponsored by IMAPS Europe. This year’s conference is chaired by Toni Mattila from Business Finland.​

More information on ​​ESTC​’s website

From9/9/2026to9/11/2026|​Helsinki, Finland​

Contact:Jean-Charles Souriau​with any questions.​​

Research engineer in electronics

Event|Grenoble Scientific Polygon, France

Europe has the expertise and skills to promote a more responsible digital sector (frugality, regulation, ethics) that creates high-quality jobs. However, mastery of data is just as crucial as mastery of materials and energy when it comes to the operability and sustainability of disruptive digital components and integrated circuits. More sustainable integrated hardware and software solutions will be discussed at the END* symposium in the field of Information & Communication Technologies (ICT)

Event|Maison Minatec, Grenoble, France

LID World Summit from 23 to 25 June offer you a front-row seat to our most recent advances. Join more than 1,250 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate!​

CEA-Leti will present a paper on Ferroelectric Memories have 2 presentations : on Neurotechnologies and Cryo-CMOS Circuits.

We’re excited to welcome you back to PCIM!

Join us to discover our latest innovations through live demonstrations, including:- Ultra thin power converter based on piezoelectric storage,- Smart multilevel converter utilizing flying capacitor topology- High Power multilevel GaN DCDC converter for fuel cell to battery voltages adaptation- Predictive maintenance on power electronic based on non invasive sensors.Focus will be put on CEA Wide Band Gap roadmap and technologies to address high demand and challenges on power supplies. It addresses different applications from data center to drones going through automotive, aeronautic, spatial, medical.

Event|Minatec, Grenoble, France

The workshop gathers scientists, engineers and industry partners to discuss advances and challenges in dry etching, plasma processing and related technologies for semiconductor, MEMS and emerging applications.