CEA-Leti researchers, as part of the Carnot ePMOS project, have advanced GaN CMOS technology by focusing on a critical component: the PMOS transistor. The “e” in ePMOS denotes an innovative design that uses electrons—rather than holes—to conduct current, building on prior patented work that already shrunk transistor dimensions. By integrating both PMOS and NMOS logic with power devices on a single GaN chip, the overall footprint of power converters can be reduced compared to traditional silicon multi-chip solutions.

The team combined numerical simulations with experimental fabrication. Simulations pinpointed parameter combinations that maximize ON-state current and minimize OFF-state leakage, with results published in a scientific journal. In parallel, researchers experimentally developed the electrical contact—a key building block—by varying the thickness and composition of an indium gallium nitride (InGaN) layer. Electrical characterization of multiple contact structures identified optimal parameters, also published in a journal.

The next step is to build and test a complete PMOS transistor guided by the simulation data. Once fully realized, the technology could enable more compact power converters, shrinking chargers for laptops, smartphones, and electric vehicles.

​​​As part of the Carnot ePMOS project, a CEA-Leti research team conducted an in-depth study of a key building block of GaN CMOS technology: PMOS transistors. Combining numerical simulations with experimental work, the project delivered significant results that pave the way for reducing the size of GaN CMOS devices for power electronics.​​

​CMOS technology is based on two types of transistors: PMOS and NMOS. These devices perform complementary functions: when one conducts current, the other blocks it, and vice versa. Together, they form the logic elements used to perform computations or control power devices.

Traditionally, these silicon-based logic elements are fabricated on a separate chip from the power device. However, by using a material such as gallium nitride (GaN), both functions can be integrated onto a single chip, helping reduce the overall size of the resulting devices.

This work was carried out within the Carnot ePMOS project, where the ​"e" refers to an innovative approach based on using electrons to conduct current within the PMOS transistor.

The research team built on previous work - which resulted in a patent - describing a GaN PMOS architecture based on electron conduction. This approach already offered a significant reduction in transistor size.

The researchers then conducted detailed numerical simulations of the device.

These simulations identified the parameter combinations delivering the best performance, namely the highest current in the ON state and the lowest leakage current in the OFF state. The results were published in a scientific journal.

In parallel, the ePMOS team conducted experimental work on one of the transistor's key technological building blocks: the electrical contact.

The researchers fabricated several contact structures while varying different parameters, including the thickness and composition of an indium gallium nitride (InGaN) layer.

Each version was then electrically characterized to determine the contact properties and identify the optimal parameters.

These experimental results were also published in a scientific journal.

The researchers now plan to build and test the complete PMOS transistor based on the simulation results.

Once fully developed, the device could be used to manufacture more compact power converters, helping reduce the size of chargers for laptops, smartphones, and electric vehicles.

Support by:https://www.lereseaudescarnot.fr/en​​​