ESSERC的宗旨是提供一个年度欧洲论坛，展示并讨论固态器件与电路的最新进展。片上系统设计的集成度正在快速提升，这得益于半导体技术的进步。因此，工艺专家、器件专家、IC设计师和系统设计师之间比以往任何时候都更需要深层次的互动。

The aim of ESSERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary.

CEA-Leti Original
摘要
CEA-Leti 将于 2026 年 9 月在西班牙 ESSERC 大会上展示其硬件安全与嵌入式系统评估创新，并联合 FAMES 与 SiNANO 举办关于 10nm 和 7nm FD-SOI 技术的专题研讨会。该机构还将在法国及东京的 Leti Innovation Days 上，探讨以 AI 芯片革命为核心的半导体创新与可持续数字技术。这一系列全球活动凸显了 CEA-Leti 在推动异构集成、新材料和边缘 AI 处理器等领域的研发合作与产业影响力。

2026年9月7日至10日，欧洲固态器件与电路会议（ESSERC）将在西班牙帕尔马举行，继续推动工艺、器件、IC设计与系统专家之间的深度交叉协作。法国CEA-Leti研究所联合CEA-List，将现场展示VASCO2演示器，呈现硅嵌入式硬件的安全创新，并通过SCIBE工具演示器展现其在嵌入式系统接口安全评估领域的实力。

在本届会议上，CEA-Leti将发表多项重要成果。9月8日上午，Fabien Roze等人将介绍基于创新晶圆键合与纳米片图形化的混合沟道CFET堆叠制造方案；同期，Ahmed Machmach等人将报告NMOS SOI源跟随器的浮体效应抑制技术，并提出3D顺序集成BSI CIS中的像素级噪声模型。9月10日上午，三项研究将同期亮相：Joaquin A. Cornejo团队发布“BumbleBee”，一款基于18纳米FD-SOI CMOS工艺、功耗仅3毫瓦的融合核Flash Attention边缘AI协处理器；Yann Beilliard等人带来集成于22纳米FDSOI后道工序（BEOL）的HZO铁电电容存储器统计特性研究；Justin Pabot等人则展示一种片上SCC拓扑，可在安全应用中降低50%功耗并将攻击痕迹缩减114倍。

9月7日，FAMES项目与SiNANO研究所将联合举办题为《FDSOI中试线洞察与展望》的半日研讨会，首次深度公开10纳米和7纳米FD-SOI技术的研发成果，这也是FAMES中试线的关键突破。联系邮箱由François Andrieu提供。

此外，CEA-Leti近期在全球多项活动中持续发声。在END*研讨会上，聚焦信息通信技术领域，探讨更加可持续的集成硬件与软件方案；第19届Leti创新日·东京站以“AI芯片革命：半导体创新规模化”为主题，CEO出席庆祝与日本产业界的合作，并在法国驻日大使馆官邸举办演讲、研讨与现场演示。在SEMICON Taiwan 2026“选择法国”展馆内，CEA-Leti将展示异构集成领域的三篇新论文。而6月于格勒诺布尔举行的LID世界峰会将迎来超过1250名半导体专业人士，全面展示其最新进展。

Summary
CEA-Leti and CEA-List will present hardware security tools (VASCO2, SCIBE) and advanced semiconductor research—including CFET stacking, FD-SOI chips, and edge AI co-processors—at ESSERC 2026, alongside a FAMES workshop revealing 10nm and 7nm FD-SOI pilot line results. The institute is also showcasing heterogeneous integration and AI-driven chip innovations at events in Tokyo and Taiwan, reinforcing European semiconductor sovereignty and global R&D collaborations.

CEA-Leti will bring a broad portfolio of advanced semiconductor research and hardware security demonstrations to multiple international events in 2026, with ESSERC in Palma de Mallorca (September 7–10) serving as the anchor conference. The institute, together with CEA-List, will showcase two hardware security tools: VASCO2, demonstrating silicon-embedded security innovations, and the SCIBE tool for security assessment of embedded systems’ interfaces.

At ESSERC’s technical sessions, CEA-Leti scientists will present five papers spanning next-generation device architectures and circuits. Highlights include a novel hybrid-channel CFET (complementary FET) stack fabricated via innovative wafer-to-wafer bonding and nanosheet patterning; a 3D sequentially integrated back-side illuminated CMOS image sensor with a source-follower pixel that mitigates floating-body effects and models pixel-level noise; BumbleBee, a 3 mW fused-kernel flash attention AI co-processor implemented in 18 nm FD-SOI CMOS; a statistical study of hafnium-zirconium-oxide-based ferroelectric capacitive memories integrated into the BEOL of a 22 nm FDSOI process; and an on-chip switched-capacitor converter topology that reduces power by 50% while expanding attack traces by 114× for security applications.

A dedicated half-day workshop on September 7, co-organized by the FAMES pilot line and the SiNANO Institute, will provide the first in-depth technical results from the development of 10 nm and 7 nm FD-SOI technologies under the “FDSOI Pilot Line Insights and Perspective” banner.

Beyond ESSERC, CEA-Leti will discuss sustainable integrated hardware and software at the END* symposium, highlight AI semiconductor scaling at Leti Innovation Days Tokyo under the theme “The AI-Chip Revolution,” and present three papers on heterogeneous integration at SEMICON Taiwan 2026 as part of the Choose France Pavilion. The institute also hosts the LID World Summit in Grenoble (June 23–25), bringing over 1,250 industry professionals together around the latest semiconductor advances. For ESSERC inquiries, contact François Andrieu.

Résumé
Le CEA-Leti et le CEA-List dévoileront à ESSERC 2026 leurs démonstrateurs de sécurité matérielle VASCO2 et SCIBE, ainsi que des résultats scientifiques majeurs sur les transistors CFET hybrides, les co-processeurs IA basse consommation en FD-SOI 18 nm et les mémoires ferroélectriques en 22 nm. Le projet FAMES et l'institut SiNANO organiseront un atelier dédié aux technologies FD-SOI 10/7 nm, illustrant les avancées de la filière européenne pour renforcer sa souveraineté semiconducteurs et répondre aux besoins de l'IA.

From 9/7/2026 to 9/10/2026Palma de Mallorca, Spain

CEA-Leti in association with CEA-List, will showcase its hardware security innovations for silicon-embedded hardware, through the VASCO2 demonstrator, as well a​s its expertise in security assessment of embedded systems’ interfaces, through the SCIBE tool demonstrator.​​

DISCOVER CEA-LETI’S MAJOR SCIENTIFIC RESULTS AT ESSERC

Tuesday September 08, 202611:00 am - 1:00​ pmSala MAGNA​​

Fabien RozeSylvain BarraudJean-Michel PediniVincent LarreyFrank FournelJean-Michel Hartmann​Karine Abadie​

Fabrication of Hybrid Channel CFET Stack by Innovative Wafer-to-Wafer Bonding and Nanosheet Patterning​​​

Tuesday September 08, 2026​11:00 am - 1:00​ pmSala GRANADOS I​

Ahmed MachmachChristoforos TheodorouSébastien PlaceThomas NassietFrederic LalanneChristian Gardin​​

Nmos SOI Source Follower Floating Body Effects Mitigation and Pixel Level Induced Noise Modeling in 3D Sequentially Integrated BSI CIS ​​​​​

Thursday September 10, 2026 10:40 am - 1:00 pmSala TURINA​

Joaquin A. CornejoFilipe PougetAmelie PoullotRaphael GrasDominique BousquetNicolas Lebouleux​Tarun Chawla​

BumbleBee: A 3 mW Fused-Kernel Flash Attention Edge AI Co-Processor in 18 nm FD-SOI CMOS​

Thursday September 10, 2026 10:40 am - 1:00 pmSala MAGNA​

Yann BeilliardLanig Le MeurSimone D’AgostinoLiam HosierSimon MartinCarine JahanFrançois AndrieuElisa Vianello ​

Statistical Study of HZO-Based Ferroelectric Capacitive Memories Integrated in 22 nm FDSOI BEOL​

Thursday September 10, 2026 10:40 am - 1:00 pmSala ALBENIZ

​Justin PabotYasser MoursyMaxime LecomteRomain Wacquez​Gaël Pillonnet​

On-Chip SCC Topologies for Security Enabling 50% Power Reduction and 114× Attack Traces​​

Meet FAMES at ESSERC 2026 in Mallorca​

On 7 September 2026, FAMES and the SiNANO Institute will host a dedicated half-day workshop entitled: “FDSOI Pilot Line Insights and Perspective” This session will be the first opportunity to present in-depth technical results from the FAMES Pilot Line on the development of 10 nm and 7 nm FD-SOI technologies. ​​

A dedicated workshop by FAMES & SiNANO Institute​

More information on ​​ESSERC’s website

From 09/07/2026 to 09/10/2026  |​Palma de Mallorca, Spain

Contact:François Andrieu​with any questions.​​

Event|Grenoble Scientific Polygon, France

Europe has the expertise and skills to promote a more responsible digital sector (frugality, regulation, ethics) that creates high-quality jobs. However, mastery of data is just as crucial as mastery of materials and energy when it comes to the operability and sustainability of disruptive digital components and integrated circuits. More sustainable integrated hardware and software solutions will be discussed at the END* symposium in the field of Information & Communication Technologies (ICT)

CEA-Leti has invested in multidisciplinary platforms with unique equipment and expertise. By leveraging advances in heterogeneous integration, new materials and photonics, we are driving semiconductor innovation and tackling the new challenges of disruptive AI markets and technologies.

During this 19th edition of Leti Innovation Days Tokyo, CEA-Leti’s CEO will celebrate R&D partnerships with its partners in Japan and explore new possibilities to support the Japanese semiconductor industry. This year’s theme is “The AI-Chip Revolution: Scaling Innovation in Semiconductors”.

High-level speakers and technical experts will present the latest advances through keynote speeches, seminars and live demos. Join us to enjoy lively networking and exchanges in a unique setting at the Residence of France in Japan.

CEA-Leti experts will be onsite at CEA-Leti's booth and available to discuss the findings of three papers on heterogeneous integration

Event|TaiNEX 1 & 2 – Taipei Nangang Exhibition Center, Taipei, Taiwan

CEA-Leti is participating in SEMICON Taiwan 2026, highlighting its latest advances in semiconductor technologies and reinforcing its long-standing commitment to scientific and industrial cooperation with Taiwan and the global semiconductor ecosystem. As part of the Choose France Pavilion, CEA-Leti contributes to promoting French excellence in technology research, innovation and technology transfer.

Event|Maison Minatec, Grenoble, France

LID World Summit from 23 to 25 June offer you a front-row seat to our most recent advances. Join more than 1,250 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate!​

AI Insight
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Core Point

CEA-Leti will present advanced semiconductor research at ESSERC 2026, including FD-SOI edge AI chips, 3D CFET stacking, ferroelectric memories, and hardware security tools, highlighting French innovation in next-generation chip design and secure integration.

Key Players
  • CEA-Leti — French semiconductor and microelectronics research institute based in Grenoble.
  • CEA-List — French institute specializing in embedded systems and security assessment, part of CEA.
  • FAMES Pilot Line — EU-led project developing 10nm/7nm FD-SOI semiconductor technologies.
  • SiNANO Institute — European academic network for nanoscale semiconductor research.
Industry Impact
  • ICT: High — secure embedded hardware and low-power SOI circuits directly improve connected devices.
  • Computing/AI: High — BumbleBee edge AI co-processor and ferroelectric memorie enable efficient, secure inference.
  • Terminals/Consumer Electronics: Medium — FD-SOI integration and power reduction benefits smartphones and IoT devices.
  • Energy: Low — on-chip security topology cuts power consumption, slightly aiding energy efficiency.
Tracking

Strongly track — CEA-Leti’s FD-SOI and security breakthroughs are central to EU semiconductor sovereignty and next-gen AI chip development.

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半导体 人工智能 网络安全
AI Processing
2026-07-28 13:34
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