CEA-Leti 平台为芯片制造商提供纳米级应变测绘

CEA-Leti Platform Offers Chipmakers Nanometre- Scale Strain Mapping

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摘要
法国 CEA‑Leti 推出一项“应变测绘”服务:利用透射电子显微镜(TEM)配合进动电子衍射(PED),通过锥形扫描获得更高质量衍射数据,并结合约 80nm 厚的 FIB 制备芯片薄片,实现器件晶格参数的高分辨测量。该方法可输出约 1nm 空间分辨率、~0.02% 精度的应变图谱,已在多台 TEM 上部署(目前 3 台),通过流程简化与加速提升样品吞吐与表征交付速度。对半导体制造与先进微电子器件的影响在于更快、更精确地量化晶格形变(应变工程),从而支持更高性能且更省电的处理器研发与质量评估。

先进微电子器件的性能,很大程度上取决于电荷能否高效传输,而这又与晶体晶格的形变密切相关。通过“应变工程”(strain engineering)有意拉伸或压缩晶格,可以提升电子流动速度;哪怕晶格间距只改变不到 1%,也可能带来更快、更省电的处理器。正因如此,CEA-Leti 近年来一直在推进材料形变的局部、定量测量,服务于当下最前沿的器件研发。

CEA-Leti 现在提供的应变映射(strain-mapping)服务,基于透射电子显微镜(TEM)和预cession electron diffraction(PED,旋转电子衍射)技术。普通电子衍射中,电子束以固定角度打到晶体上,常因动态散射产生复杂图样;PED 则让电子束沿锥形轨迹旋转扫描,记录多个取向下更完整的衍射信息,从而获得更高质量的数据,并进一步转换为应变图。

整个流程从样品制备开始:先用聚焦离子束(FIB)制备超薄 lamella,也就是芯片的横截面薄片,厚度约 80 nm。样品准备好后,被送入配备 PED 模块的 TEM 显微镜中,通过扫描衍射在器件不同区域测量晶体晶格参数,实现高空间分辨率的局部分析。

这套技术可提供 1 nm 空间分辨率、约 0.02% 精度的应变图,使 CEA-Leti 跻身全球纳米尺度计量领域的领先者之列。为了提高通量并更高效利用设备,相关流程还被尽可能简化和加速,因此表征请求的周转时间也更短。

目前,CEA-Leti 已有 3 台 TEM 配备 PED 测量能力,这不仅让实验室能够处理更多样品,也使这项服务可以向更多合格的显微镜操作人员开放。该项目并非孤立推进,而是依托团队成员在基础研究与应用工程之间的协同:正是这种结合,把一种实验性方法转化成了可日常使用的常规表征服务。

Summary
CEA‑Leti has expanded its strain‑mapping service for advanced microelectronic devices, using transmission electron microscopy with precession electron diffraction (PED) to measure crystal lattice deformation that drives faster, more power‑efficient processors. The workflow uses ~80 nm‑thick FIB‑milled lamellae and PED in a TEM to generate high‑quality diffraction data, producing strain maps with ~1 nm spatial resolution and ~0.02% precision, while improving throughput and turnaround time. With three TEM systems now equipped for PED, CEA‑Leti can process more samples and broaden access for qualified microscopists, turning an experimental method into a routine metrology service.

CEA-Leti has turned strain mapping into a practical characterization service for chipmakers, using transmission electron microscopy (TEM) and precession electron diffraction (PED) to measure local lattice deformation at the nanometre scale. The work matters because the performance of advanced microelectronic devices depends heavily on efficient charge transport, which is strongly influenced by crystal-lattice strain. By deliberately stretching or compressing the lattice, strain engineering can speed electron flow and improve processor performance and power efficiency, even with changes in lattice spacing of only a fraction of a percent.

The service begins with ultra-thin lamellae, about 80 nm thick, cut from a chip cross-section using focused ion beam (FIB) milling. These specimens are then inserted into a TEM fitted with a PED module. Unlike ordinary electron diffraction, where a fixed beam angle can produce complex patterns because of dynamic scattering, PED rotates the beam in a conical sweep and captures diffraction data across dozens of orientations. That produces cleaner, more complete patterns that can be converted into strain maps.

CEA-Leti says the method can deliver 1 nm spatial resolution with about 0.02% precision, putting the lab among the world leaders in nanoscale metrology. The workflow has also been simplified and accelerated to improve throughput and shorten turnaround times for characterization requests. Three TEMs are now configured for PED measurements, increasing sample capacity and making the service available to more qualified microscopists.

Bernier stressed that the platform was made possible by the combined expertise of the team, highlighting the link between fundamental research and application-driven engineering. That collaboration helped transform an experimental technique into a routine industrial service for measuring material deformation in cutting-edge devices.

Résumé
Le CEA‑Leti annonce une offre de « strain‑mapping » pour l’ingénierie de contrainte des semi‑conducteurs, basée sur la microscopie électronique en transmission (TEM) avec diffraction précession (PED) afin de mesurer localement les déformations du réseau cristallin, déterminantes pour la vitesse et l’efficacité des processeurs. La méthode, réalisée sur des lamelles ultra‑fines préparées par FIB (≈80 nm), fournit des cartes de contrainte avec une résolution spatiale de 1 nm et une précision d’environ 0,02 %, tout en étant simplifiée pour augmenter le débit : trois microscopes TEM sont désormais équipés. En renforçant la métrologie à l’échelle nanométrique et le temps de réponse des demandes de caractérisation, le CEA‑Leti consolide sa position parmi les leaders mondiaux et facilite l’accès du service à davantage de microscopistes.

​​​​​​The performance of advanced microelectronic devices depends especially on the efficient transport of electrical charges. These transport properties are strongly related to deformation of the crystal lattice.

Strain engineering, which involves deliberately stretching or compressing a crystal lattice, is used to boost the speed of electron flow in a device. Even a fraction of percent change in lattice spacing can translate into faster and more power-efficient processors. That is why at CEA-Leti we have been working in recent years on the local and quantitative measurement of material deformations, which are at the heart of today’s cutting-edge devices.​​​​

CEA‑Leti's strain‑mapping service uses transmission electron microscopy (TEM) to carry out precession electron diffraction (PED). In ordinary electron diffraction the beam hits the crystal at a fixed angle, often producing complex patterns because of dynamic scattering. PED solves that by rotating the beam in a conical sweep, recording a more complete diffraction pattern over dozens of orientations. The result is higher-quality diffraction data that can be turned into strain maps.

The workflow starts with ultra‑thin lamellae—cross‑sections of a chip that are roughly 80 nm thick— prepared using focused ion beam (FIB) milling.

Once the specimen is ready, it is inserted into a TEM microscope equipped with a PED module. Scanning diffraction allows the lab to measure the lattice parameters of the crystal with high spatial resolution in different regions of a device.

The technique delivers strain maps with 1 nm spatial resolution and ~ 0.02 % precision, which places CEA-Leti among the world's leaders in nanoscale metrology.

The technique has been simplified and accelerated where possible to enable higher throughput and make better use of the instruments. The result is a faster turnaround time for characterization requests.

Three TEMs are now equipped to perform PED measurements, allowing CEA-Leti to handle a larger volume of samples and making the service accessible to more qualified microscopists.

The project didn't happen in isolation. Bernier​​ emphasizes the combined expertise of the team members that made it possible:

That partnership between fundamental research and application‑driven engineering helped turn an experimental methodology into a practical, routine characterization service. ​

AI Insight
Core Point

CEA‑Leti expanded its TEM precession electron diffraction (PED) strain‑mapping service to deliver ~1 nm spatial resolution and ~0.02% precision, enabling chipmakers to quantify lattice deformation that drives performance and power efficiency.

Key Players

CEA‑Leti — microelectronics R&D lab in France offering TEM/PED nanoscale strain metrology services to chipmakers.

Bernier (CEA‑Leti) — spokesperson highlighting the team’s fundamental-to-applied engineering collaboration.

Industry Impact
  • Computing/AI: Medium — better device characterization can improve next‑gen processor efficiency and speed via strain engineering.
  • ICT: High — high-precision nanoscale metrology reduces uncertainty in advanced semiconductor process development.
Tracking

[Strongly track] — scaling PED-equipped TEM capacity and throughput can materially affect semiconductor characterization workflows and adoption.

Highlights
Tech Breakthrough Local Research
Related Companies
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Categories
半导体 科研
AI Processing
2026-09-03 23:02
openai / gpt-5.4-nano