脉冲整形抑制SOT-MRAM中的本征回切

Pulse Shaping Suppresses Intrinsic Back-Switching in SOT-MRAM

Spintec News by Daria Gusakova 2026-07-05 19:30 Original
摘要
Spintec与Antaios合作发现,SOT-MRAM在高电流下会因内在反向切换机制导致写入概率下降或振荡,通过延长脉冲下降时间(2至4纳秒)可有效抑制该现象,显著拓宽可靠写入窗口。该研究在β-W霍尔交叉结构和完整SOT-MRAM单元上均得到验证,对提升存储器可靠性和推动技术成熟具有关键意义。

自旋轨道力矩(SOT)MRAM在高写入电流下会表现出反常行为:随着电流幅度增加,写入概率可能降为零甚至出现振荡。Spintec实验室与Antaios公司合作,证实该现象源于一种固有且高度决定论的回跳机制,并展示了通过精细调控写入脉冲的下降时间,可显著拓宽可靠写入窗口。

研究团队在β-W霍尔交叠结构上制备了约60 nm的CoFeB垂直磁化柱,并在x、y、z方向施加磁场,系统测量了纳秒脉冲写入的误码率(WER)随电流变化的图谱。所有WER图均清晰呈现出三个区域:无翻转区、低误码的确定性前向翻转区,以及磁化返回初始态的高误码区——这有力证明了回跳是系统动力学必然结果,而非随机噪声。该现象在使用10 ns实际写入脉冲时即可观测,且在不同器件配置中复现:包括β-W霍尔交叠上的100 nm CoFeB柱(0.9 nm厚)和完整SOT-MRAM单胞(75 nm磁性隧道结交叠在130 nm宽、4 nm厚的β-W SOT轨道上),突显其对电路级运行的潜在影响。

宏观自旋模拟完整重现了WER图谱,并揭示了物理机制:大电流下自旋轨道力矩将磁化推至面内不稳定平衡点附近;脉冲结束后,弛豫过程中的微小热涨落可能使磁化退回初始态,具体取决于力矩的平衡状态。基于这一认识,团队采用脉冲整形策略在不改变材料的前提下抑制回跳:延长脉冲下降时间可使力矩在弛豫阶段持续作用,引导磁化远离不稳定点。实验结果显示,将下降时间从2 ns增至4 ns可有效消除回跳,扩大前向翻转窗口;在完整的SOT-MRAM单胞上,该方法实现了低于10⁻⁶的WER,获得了可靠写入所需的电流窗口。

该研究为SOT-MRAM迈向高可靠电路级写入提供了关键方案。相关成果发表于《Physical Review Applied》(论文标题:Intrinsic back‑switching phenomenon in spin‑orbit torque MRAM devices),并获欧盟“地平线2020”MSCA ITN SPEAR项目(资助号955671)、奥弗涅-罗讷-阿尔卑斯大区Pack Ambition Recherche计划(19-009938-01-MAPS)及RENATECH/PTA(ANR-22-PEEL-0015)支持。联系作者为Gilles Gaudin。

Summary
Researchers from Spintec and Antaios identified that an intrinsic, deterministic back-switching mechanism causes write failures in SOT-MRAM at high currents, and they showed that lengthening the write pulse’s fall time effectively suppresses this effect, significantly widening the reliable writing window. The work, demonstrated on both test pillars and full SOT-MRAM cells, was published in Physical Review Applied and provides a circuit-level solution to a key reliability barrier, advancing the viability of SOT-MRAM for high-speed, high-endurance cache replacement near processors.

Spin–orbit-torque (SOT) MRAM, prized for its high endurance and sub‑nanosecond switching, faces a reliability hurdle: high‑current write pulses can cause write probability to collapse or oscillate. Collaborating with Antaios, Spintec researchers have now revealed that this phenomenon stems from an intrinsic, largely deterministic back‑switching mechanism, and they demonstrate that lengthening the pulse fall time effectively suppresses it, substantially widening the viable write window.

The team mapped write‑error rate (WER) as a function of nanosecond SOT‑pulse amplitude on ~60‑nm CoFeB pillars on β‑W Hall crosses, applying magnetic fields along three axes. The maps consistently show three regimes: no switching, a low‑WER forward‑switching zone, and a high‑WER back‑switching region where the bit returns to its initial state. This pattern, observed on both 100‑nm pillars and full single‑cell MTJs (75‑nm dot on a 130‑nm‑wide β‑W track) with practical 10‑ns pulses, confirms that back‑switching is a systematic dynamical outcome, not random noise.

Macrospin simulations explain the behavior: strong spin‑orbit torques drive the magnetization near an unstable in‑plane equilibrium; after the pulse, small thermal fluctuations can trigger relaxation back to the original state. Rather than modifying materials, the researchers tackled the problem with pulse shaping. By increasing the fall time from 2 ns to 4 ns, the torques remain active during relaxation, steering the magnetization safely away from the instability. Experimentally, this widened the forward‑switching current window and, on a full SOT‑MRAM cell, yielded a WER below 10⁻⁵ across an extended current range.

The work, supported by EU MSCA ITN SPEAR (Grant 955671), Région Auvergne‑Rhône‑Alpes (19‑009938‑01‑MAPS), and RENATECH/PTA (ANR‑22‑PEEL‑0015), is detailed in *Phys. Rev. Appl.* 24, 064038 (2025) and open‑access via HAL (hal‑05411536).

Résumé
Des chercheurs de Spintec, en collaboration avec Antaios, ont découvert que le phénomène de retour à l'état initial (back-switching) dans les mémoires SOT-MRAM est un mécanisme intrinsèque et déterministe, et non aléatoire. En ajustant la forme de l'impulsion d'écriture, notamment en allongeant le temps de descente, ils ont réussi à supprimer ce phénomène et à élargir la fenêtre d'écriture fiable. Cette avancée, menée par K. Ray, J. Vigier, P. Usé et Gilles Gaudin, est cruciale pour la maturation de cette technologie destinée à remplacer les mémoires proches des unités de calcul.

Spin–orbit-torque (SOT) MRAM writing exhibits an unusual current dependence: at high current amplitudes, the write probability can drop to zero or even oscillate as the current increases. In collaboration with Antaios, we showed that this behavior originates from an intrinsic, largely deterministic back-switching mechanism, and we demonstrated that tailoring the pulse fall time significantly widens the reliable write window.

Experimental WER versus SOT write current for 10-ns pulses. (a) 100-nm CoFeB(0.9 nm) pillars on β-W Hall crosses, measured at HX=950Oe for pulse fall times of 2, 3, and 4 ns. (b) 75-nm MTJ dot on a 130-nm-wide β-W(4 nm) SOT track, measured at Hx=800Oe with a 2-ns fall time.

SOT-MRAM is particularly attractive for replacing the memories closest to processing units, as it combines high endurance with sub-nanosecond switching times. Reliable writing is therefore essential for this technology to scale and mature. However, perpendicularly magnetized SOT-MRAM devices may enter a back-switching regime in which increasing the current causes the bit to relax back to its initial state. We studied ~60-nm CoFeB pillars on β-W Hall crosses and mapped the write-error rate (WER) as a function of nanosecond SOT-pulse amplitude under magnetic fields applied along x, y, and z. These WER maps consistently reveal three regions: no switching, deterministic forward switching (low WER), and a high-WER zone where the magnetization returns to the starting state. This provides clear evidence that back-switching is a systematic dynamical outcome rather than random noise. Importantly, the effect is observed with practical nanosecond-scales write pulses and is reproduced across device configurations, from 100-nm pillars on β-W Hall crosses to a full SOT-MRAM single cell (MTJ dot on a W SOT track), highlighting its relevance for circuit-level operation.

Realistic macrospin simulations reproduce the maps and clarify the mechanism: at large currents, spin-orbit torques drive the magnetization close to an energetically unstable in-plane equilibrium; after the pulse, small thermal fluctuations during relaxation can send it back to the original state, depending on the torque balance. Guided by this picture, we mitigate back-switching without changing materials by shaping the write pulse. Lengthening the fall time keeps the torques active during relaxation and steers the magnetization away from the unstable point. Experimentally, increasing the fall time (2→4 ns) suppresses back-switching and widens the forward-switching window; on a complete SOT-MRAM single cell, this approach achieved WER

Team: Spinorbitronics

Collaborations: Antaios

Funding: EU Horizon 2020 MSCA ITN SPEAR (Grant 955671), Région Auvergne-Rhône-Alpes Pack Ambition Recherche (19-009938-01-MAPS), and RENATECH/PTA support (ANR-22-PEEL-0015)

Further reading: Intrinsic back-switching phenomenon in spin-orbit torque MRAM devices, K. Ray, J. Vigier, P. Usé , S. Martin, N. Lefoulon, C. Bouard, M. Drouard, G. Gaudin, Phys. Rev. Appl. 24, 064038 (2025).

Open access: hal-05411536

Contact: Gilles Gaudin

The post Pulse Shaping Suppresses Intrinsic Back-Switching in SOT-MRAM appeared first on Spintec.

AI Insight
核心点

通过延长写入脉冲下降沿,成功抑制了SOT-MRAM在高电流下的固有回切现象,大幅拓宽可靠写入窗口,这对该技术替代近处理器缓存至关重要。

关键参与者
  • Spintec — 法国自旋电子学实验室,主导器件物理研究与宏自旋模拟。
  • Antaios — 法国MRAM初创公司,提供SOT-MRAM单细胞器件进行合作验证。
行业影响
  • ICT: 高 — 直接提升SOT-MRAM写入可靠性,加速其替代SRAM/DRAM缓存。
  • 计算/AI: 中 — 可靠SOT-MRAM可推动存内计算与AI加速器发展。
  • 终端/消费电子: 中 — 若量产,可提升移动设备高速缓存性能与耐久性。
追踪

强烈追踪 — 该脉冲工程方案无需更换材料,解决了SOT-MRAM走向量产的关键动态可靠性瓶颈,可能成为行业标准提升方案。

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2026-07-05 23:08
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