Researchers from CEA-Leti, Spintec in Grenoble, and C2N/Université Paris-Saclay have demonstrated a hybrid nanoelectronic Ising machine that combines hafnium-oxide resistive random-access memory (ReRAM) memristors with stochastic magnetic tunnel junctions (SMTJs) to tackle hard combinatorial optimization problems. The work, published in *Nature Communications* under the title “Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine,” is presented as a hardware route toward faster, more compact, and more energy-efficient optimization accelerators.

Ising machines are specialized systems that search for low-energy states corresponding to good solutions across huge combinatorial spaces. In this prototype, the researchers implemented key steps of a local-search algorithm directly in nanodevice hardware, reducing data movement and the explicit digital-instruction overhead typical of conventional approaches. The goal is to make optimization more efficient for workloads where better use of time, energy, and resources matters across industries.

The paper’s first authors, Mohammed Akib Iftakher, a doctoral researcher at CNRS, C2N and Université Paris-Saclay, and Hugo Levices, a doctoral researcher at CEA-Leti, said the project shows that hybrid nanotechnologies can be combined into a functioning optimization accelerator rather than treated as separate components. Because ReRAM, magnetic tunnel junctions and CMOS circuitry are all compatible with advanced integration, the architecture points toward compact hardware for local-search optimization.

A central challenge in such machines is managing stochasticity: the random fluctuations needed to explore candidate solutions. Early in the search, high randomness helps avoid local minima; later, the system must become more stable to converge. The team’s key contribution is an intrinsic annealing mechanism in which ReRAM devices store the problem graph—the links describing how variables influence one another—while SMTJs act as probabilistic yes/no variables driven by thermal noise. By adjusting the read voltage of the ReRAM array, randomness gradually decreases during the search, reducing the need for a separate control layer.

The current prototype still uses external feedback for measurement, but the architecture is designed to move toward a fully integrated system with less data movement and fewer digital instructions. Tested on benchmark problems, it consistently found the global optimum for a 24-vertex weighted MAX-CUT instance and a 10-vertex, three-color graph-coloring problem, with all measurements taken at room temperature and zero magnetic field.

The authors say the sequential prototype already validates the concept, but a fully integrated version could be much faster by exploiting massive parallelism, nanosecond-scale switching, and direct coupling between the crossbar and the spins, eliminating analog-to-digital conversion delays. Both ReRAM and SMTJs are CMOS-compatible and integrated in back-end-of-line (BEOL) layers, aligning with 3D integration trends needed for scaling.

The team now plans to move beyond proof-of-concept toward larger, more scalable systems, with priorities including closer integration of control electronics—ideally on-chip or in 3D stacks—testing larger problem sizes, and enabling true parallel operation. Future benchmarking will focus on speed and energy consumption versus conventional computing to quantify the performance gains.

Communiqué de presse|Actualité|Nouvelles technologies

​​​Nature Communications Paper Opens Hardware Path TowardEnergy-Efficient Optimization Accelerators, Combining ReRAM Devices ​

GRENOBLE, France - September 8, 2026 - Researchers from CEA-Leti andSpintecin Grenoble, and fromC2N/Université Paris-Saclay, have demonstrated a hybrid nanoelectronic Ising machine that combines memristors implemented as hafnium-oxide resistive random-access memory (ReRAM) devices with stochastic magnetic tunnel junctions (SMTJs) to solve hard combinatorial optimization problems.

Reported inNature Communications, the article, "Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine,"introduces an intrinsic annealing mechanism that could pave the way for more compact, faster, and energy-efficient hardware accelerators. (Note: Paper title kept as published.)

Ising machines are specialized hardware accelerators designed to search for optimal solutions among vast numbers of possibilities. They operate by repeatedly updating binary variables until the system reaches a low-energy configuration that achieves a good compromise between the problem constraints.

Compared with conventional implementations of local-search optimization, the research team's architecture aims to reduce data movement and explicit digital-instruction overhead by implementing key operations with the physical properties of nanodevices.

The research addresses combinatorial optimization - a critical computational task involving finding the best choice among countless combinations of possibilities. Efficiency gains in this area can translate into saved time, energy, and resources across industries. Relevant application domains include:

In this project, the machine implemented key operations of a local-search algorithm using dedicated hardware primitives, reducing the amount of data movement and the number of explicit digital instructions required to execute the algorithm.

The two first authors of the paper, Mohammed Akib Iftakher, a doctoral researcher at CNRS, C2N & Université Paris Saclay, and Hugo Levices, doctoral researcher at CEA-Leti, explained:

The project also demonstrated that hybrid nanotechnologies can be combined into a working optimization accelerator, rather than treated as separate building blocks. Because ReRAM devices, magnetic tunnel junctions, and CMOS circuitry are compatible with advanced integration, the work points toward compact, fast, and energy-efficient hardware for local-search optimization.

A primary challenge in optimization hardware is controlling "stochasticity" - the random fluctuations needed to explore possible solutions. Early stages require high randomness to avoid getting stuck in local minima, while later stages require stability to converge on a solution.

The team demonstrated a system in which the two nanotechnologies work together naturally.  ReRAM devices store the problem graph–the links describing how variables influence each other - while SMTJs act as probabilistic yes/no variables that fluctuate due to thermal noise. Because these two elements are closely coupled, adjusting the read voltage of the ReRAM devices array progressively reduces randomness during the search, providing intrinsic annealing with minimal additional circuitry.

This close coupling provides a natural pathway for annealing without needing a separate, heavy control layer for every update step. While the current prototype utilizes external feedback for measurement, the underlying architecture points toward a fully integrated version that minimizes data movement and digital instruction overhead.

The prototype was tested on concrete graph-optimization benchmarks, consistently finding the global optimum for a 24-vertex weighted MAX-CUT problem and a 10-vertex, three-color graph-coloring problem. All measurements were performed at room temperature and zero magnetic field.

While the current device operates with sequential updates, the authors highlight significant potential for speed improvements in a fully integrated version. By exploiting massive parallelism, utilizing nanosecond-scale switching speeds, and enabling direct coupling between the crossbar and spins - eliminating analog-to-digital conversion delays -the approach could eventually be orders of magnitude faster than current electronic Ising machines.

This work bridges two complementary nanotechnologies-ReRAM for dense storage and SMTJs for thermally driven randomness-into a single computing architecture. Both components are CMOS-compatible and integrated in back-end-of-line (BEOL) layers, supporting the vertical 3D integration trends essential for scaling.

The team plans to move from proof-of-concept experiments to more scalable systems. Priority steps include integrating control electronics closer to the devices-ideally on the same chip or in 3D stacks-​testing larger problem sizes, and exploiting true parallel operation. Future work will focus on benchmarking speed and energy consumption against conventional computing approaches to quantify performance gains.